1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device capable of storing binary or trinary or more data in a memory cell and to an IC memory card using the same.
2. Description of the Related Art
In a nonvolatile semiconductor memory device such as a flash memory, a binary type memory cell structure for storing data taking two values of "0" and "1" in one memory cell transistor is usual.
Along with the recent demands for increasing the capacity of semiconductor memory devices, a so-called multi-level type nonvolatile semiconductor memory device for storing trinary or more data in one memory cell transistor has been proposed (refer to for example "A Multi-Level 32 Mb Flash Memory" '95 ISSCC P132 on).
When a nonvolatile semiconductor memory device capable of storing multi-level data, including binary data, in this way is used as data storage, each page is constituted by a data region and a spare region, and the method of use of the spare region is left to the user.
FIG. 10 is a block diagram of an example of the configuration of a nonvolatile semiconductor memory device of the related art.
This nonvolatile semiconductor memory device 10 is constituted by, as shown in FIG. 10, a memory array 11, a main decoder 12, a sub decoder 13 and a multi-level use latch and sense amplifier circuit (LS) 14.
The memory array 11 is constituted by a data region 111 and a spare region 112. For example, management information of the data stored in the data region 111 is stored in the spare region 112.
The data region 111 and the spare region 112 are driven by the single main decoder 12.
FIG. 11 is a circuit diagram of a concrete example of the configuration of the memory array 11 and the main decoder 12. In FIG. 11, a NAND type flash memory is shown as an example.
As shown in FIG. 11, in the memory array 11, memory strings STRG0, STRG1, . . . each constituted by eight serially connected memory transistors M0 to M7 and two selection transistors ST0 and ST1 serially connected to the two ends thereof are arranged in the form of a matrix.
For example, the string STRG0 is allocated as the data region 111, and the string STRG1 is allocated as the spare region 112.
The selection transistor ST0 connected to the drain of the memory transistor M0 of the memory string STRG0 is connected to a bit line BL0, and the selection transistor ST0 connected to the drain of the memory transistor M0 of the memory string STRG1 is connected to a bit line BL1.
Further, the selection transistors ST1, to which the memory transistors M7 of the memory strings STRG0 and STRG1 are connected, are connected to a common source line SL.
Further, gate electrodes of the memory transistors of the memory strings STRG0 and STRG1 arranged in the same row are connected to common word lines WL0 to WL7, the gate electrodes of the selection transistors ST0 are connected to a common selection gate line DSG0, and the gate electrodes of the selection transistors ST1 are connected to a common selection gate line SSG0.
The main decoder 12 is constituted by a main row decoder 120, a transfer gate group 130 which is controlled in its conductive state by the main row decoder 120, word line and selection gate line use drive voltage supply lines VCG0 to VCG7, VDSG, and VSSG from a sub decoder (not illustrated), and a supply line Vpp1 of a program voltage Vpp connected to the main row decoder 120.
The transfer gate group 130 is constituted by transfer gates TW0 to TW7, TD0, TS0, and TF0.
Specifically, the transfer gates TW0 to TW7 operationally connect the word lines WL0 to WL7 and the drive voltage supply lines VCG0 to VCG7 in accordance with an output signal BSEL of the main row decoder 120, respectively. The transfer gates TD0 and TS0 similarly operationally connect the selection gate lines DSG0 and SSG0 and the drive voltage supply lines VDSG and VSSG in accordance with the output signal BSEL of the main row decoder 120.
Further, the transfer gate TF0 is provided for preventing the selection gate line DSG0 from floating in the case of non-selection and connects the selection gate line DSG0 to a ground line at the time of non-selection.
Further, the main row decoder 120 is constituted by a 3-input NAND circuit NA1, inverters INV1 and INV2, a 2-input NAND circuit NA2, depletion type NMOS transistor NT1, enhancement type NMOS transistors NT2 (low threshold voltage) and NT3, and a capacitor C1 formed by connecting the source and the drain of the MOS.
In such a configuration, the reading of the data of the memory transistors M3 of the memory strings STRG0 and STRG1 and the writing of the data into the memory transistors M3 are carried out as follows.
At the time of reading, a ground voltage GND (0V) is supplied to the drive voltage supply line VCG3 by a sub decoder (not illustrated), P5V (for example 4.5V) is supplied to the drive voltage supply lines VCG0 to VCG2 and VCG4 to VCG7 and the drive voltage supply lines VDSG and VSSG, P5V is supplied to the program voltage supply line Vpp1, and the ground voltage 0V is supplied to the source line SL.
The active address signals X1, X2, and X3 are input to the main row decoder 120, while the output signal BSEL of the main row decoder 120 is output at a level of P5V+.alpha..
By this, the transfer gates TW0 to TW7 and TD0 and TS0 of the transfer gate group 130 become conductive. At this time, the transfer gate TF0 is held in the non-conductive state.
As a result, the selection transistors ST0 and ST1 of the memory strings STRG0 and STRG1 become conductive state, and the data is read to the bit lines BL0 and BL1.
At the time of writing, a high voltage, for example, 20V, is supplied to the drive voltage supply line VCG3 selected by the sub decoder 13, an intermediate voltage (for example, 10V) is supplied to the drive voltage supply lines VCG0 to VCG2 and VCG4 to VCG7, a power supply voltage V.sub.CC (for example 3.3V) is supplied to the drive voltage supply line VDSG, the ground voltage GND is supplied to the drive voltage supply line VSSG, and, for example, 20V is supplied to the program voltage supply line Vpp1.
Further, the ground voltage GND is supplied to the bit line BL0 to which the memory string STRG0 having the memory transistor M3 to be written, and the power supply voltage V.sub.CC is supplied to the bit line BL1 to which the memory string STRG1 having the memory transistor M3 to be inhibited from being written is connected.
The active address signals X1, X2, and X3 are input to the main row decoder 120, while the output signal BSEL of the main row decoder 120 is output at a level of 20V+.alpha..
By this, the transfer gates TW0 to TW7 and TD0 and TS0 of the transfer gate group 130 become conductive state.
As a result, the write voltage 20V is supplied to the selection word line WL3, and a pass voltage (intermediate voltage) Vpass (for example 10V) is supplied to the non-selected word lines WL0 to WL2 and WL4 to WL7.
By this, the selection transistor ST0 of the memory string STRG1 becomes cut-off and channel portions of the memory string STRG1 to which the memory transistor to be inhibited from being written is connected become floating. As a result, the voltages of these channel portions are boosted mainly by capacitor coupling with the pass voltage Vpass supplied to the non-selected word line and rise up to the write inhibit voltage, whereby the writing of data to the memory transistor M3 of the memory string STRG1 is inhibited.
On the other hand, the channel portion of the memory string STRG0 to which the memory transistor to be written is connected is set at the ground voltage GND (0V), the data is written in the memory transistor M3 by the voltage difference from the write voltage 20V supplied to the selected word line WL3, and the threshold voltage shifts in a forward direction and becomes, for example, from -3V of the erasing state to about 2V.
Turning now to the problem to be solved the invention, data storage purpose flash memories of large capacities such as 64 Mbit NAND type flash memories have recently started to appear. Along with this, the market for digital still cameras and other large capacity products has become more active.
Integrated circuit (IC) memory cards using flash memories as storage media have been proposed and marketed and are being used in some digital still cameras. Almost all of the flash memories appearing in the market however are presently binary in format. The specifications are determined based on binary characteristics.
In the case of a flash memory, as mentioned above, an increase of capacity is achieved by miniaturization of the design rule. In addition, this may be realized by a so-called multi-level structure storing a plurality of data in a single cell.
Such a multi-level structure has the merit that two, three, or more times the capacity can be realized by the same generation, but there is a disadvantage that the reliability becomes lower since the distribution of Vth is made narrower.
Further, in NAND and other flash memories for data storage, the "page" serving as the write/read unit is constituted by a data region and a spare region. The method of use of the spare region is left to the user.
When the spare region is used as a management region for a certain data region, a high reliability is required in the management region.
In such a situation, a certain degree of reliability can be secured in the case of binary data, but the reliability of retention etc. is lowered in the case of multi-level data.
Further, in a NAND type flash memory, a function of additional writing (function of additionally writing data in part of a page without erasing which writes "1" into parts for which the additional writing is not carried out) is supported, but this function is possible only for binary data. If it is intended to perform additional writing in a multi-level flash memory, a high voltage is also applied to the gates of the cells for which the data is not to be changed on the same word line, so there is a possibility that the threshold voltage Vth of the cells for which the data is not to be rewritten will change due to the disturbance.
In the case of binary data, the potential difference between the upper limit/lower limit of the distribution and the judgement level is wide, so the data can be correctly read even if the distribution lightly changes, but this potential difference is arrow in the case of multi-level data so the possibility of causing an erroneous reading is high. For this reason, the method of the additional writing can not be supported in the case of multi-level data.
Further, if the management data arranged in the spare region is also arranged in the data region for the purpose of package management etc., since the data region is designed to handle multi-level data in the write/read structure, the management data will also end up being stored in the form of multi-level data. Therefore, management data for which a high reliability is required cannot be arranged in the data region.